The present invention generally relates to interfaces between digital data processing system busses. More particularly, the invention is directed to apparatus and methods for controlling the transfer of data from one bus to another bus, where the bus data widths and bus frequencies differ.
The designs of digital computers and workstations continue to evolve at a rapid pace as new processors (microprocessors/CPUs) become available and are integrated with input/output (I/O) resources into advanced versions of such is systems. Though the widths of the multiple busses commonly present in such systems often vary from model to model, the prevailing and evolutionary changes between models tend to be associated with the clock rates of the processors. Namely, it is very common for a fundamental system design to be upgraded with faster processors in half year or less increments of a model's life cycle. The problem is that the system boards are designed with busses and associated hardware which operate over a first relative frequency range while the processor clock frequencies vary over a second range of fundamentally higher frequencies. This has created a need for a versatile interface system, one which efficiently mates input/output bus architectures with processor bus architectures, as processor clock frequencies change.
The present invention is particularly suited to the transfer of data between busses, when the transfer is accomplished in a burst protocol using a memory controller which provides data in beats at a set pace. For example, the interface may be between a processor bus (having a processor, a main memory, and a memory controller connected thereto), and an I/O bus, such as the commercially prevalent peripheral control interface (PCI) bus. In such context it is common to have a PCI bus master use a burst protocol to rapidly access successively stored data in the main memory. However, since processor clock frequencies and memory access latencies change frequently, while the basic PCI bus standard is relatively fixed, there is a need for a flexible interface.
Controlling the transfer of data in burst mode from a memory on a processor bus to a bus master on a PCI bus has typically been accomplished in one of two ways. The first technique involves the use of an interlock, pacing the transfer of each individual word of data from the memory to the PCI bus master. The interlock requires that the PCI bus master wait when the data is not available, and continue the data read operations when the data becomes available. This technique unfortunately requires complex interlock control logic and "wait state" delays to accomplish the necessary handshaking. The logic is affected by,the PCI bus master capabilities, the sizes of the data bus widths and the different main memory access latencies.
The second method of controlling data flow between busses during a burst mode read from processor memory involves the use a multiword buffer to store the passed blocks of data. In this practice, the PCI bus master accesses the buffer when the buffer becomes full. This technique avoids basic problems attributable to evolutionary changes in the clock frequency of the CPU bus and is simple to control. However, it hinders performance because the PCI bus master is required to wait until the entire block of data is buffered before beginning access. Furthermore, the "wait" imposed oh the PCI bus master may violate the PCI specification if the period exceeds the maximum permitted for data latency.
What is needed is a flexible bus interface system which can optimize burst mode data transfers from a memory on a processor bus to a PCI type I/O bus master, taking into account differences in bus width, differences in the bus clock frequencies, the effects of memory access latency, and evolutionary changes in the processor bus clock frequencies.